1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with high integration. More particularly, this invention pertains to an EEPROM (Electrically Erasable Programmable Read Only Memory) using a ferroelectric substance as a memory element.
2. Description of the Related Art
It is known that EEPROMs have been developed which accumulate potentials by the hysteresis of a ferroelectric substance.
FIG. 4 illustrates a method of fabricating a conventional EEPROM of this type. As shown in FIG. 4A, after a device isolation area (not shown) is formed on the surface of a P type silicon substrate by an LOCOS (Local Oxidation) method, the resultant structure is oxidized using oxygen diluted by hydrochloric acid (HCl) or argon (Ar), thereby forming a silicon oxide film which will serve as a gate insulating film 2.
Then, a polycrystalline silicon film is deposited on the gate insulating film 2 using an LPCVD (Low-Pressure Chemical Vapor Deposition) method, and patterned, forming a gate electrode 3 as a word line. With the polycrystalline silicon film constituting this gate electrode 3 used as a mask, phosphorus (P) or arsenic (As) is ion-implanted in the P type silicon substrate 1, then thermally diffused, thus forming a source or drain region 4.
After a silicon oxide film serving as a interlayer insulating film 5 is deposited using a CVD (Chemical Vapor Deposition) method, the tungsten (W) is vapor-deposited on the silicon oxide film and patterned to be a first electrode 9 as shown in FIG. 4B. Then, a ferroelectric substance layer 6 is formed on the first electrode 9 through magnetron sputtering using a PZT-based ceramic target. PbSr{(YNb)TiZr}O.sub.3 +Sb.sub.2 O.sub.3 which has a titanate and a zirconate as main substances is used as the PZT-based ceramic, and with the substrate heated to 300.degree. C., the ferroelectric substance layer 6 is formed 4500 .ANG. thick at a speed of 600 .ANG./hr.
Thereafter, tungsten (W) is vapor-deposited as a second electrode 10 of the ferroelectric substance layer 6, and this layer 6 and the electrodes 9 and 10 are patterned, followed by deposition of an interlayer insulating film 7 by the CVD method, as shown in FIG. 4C. Then, as shown in FIG. 4D, multiple contact holes 11 are formed in the interlayer insulating film 7, etc., and aluminum (Al) is deposited on the resultant structure by a sputtering method, and patterned, followed by formation of metal wires 8, which are connected to the source or drain region 4, the gate electrode 3, and the first and second electrodes 9 and 10 both connected to the ferroelectric substance layer 6. These metal wires 8 which are connected to the gate electrode 3 and the first electrode 9 are not illustrated.
In an EEPROM cell having the aforementioned ferroelectric substance, after the formation of the second electrode 10, this electrode 10 is coupled to the source or drain region 4 of a transistor using the metal wire 8. Because of the connection of the second electrode 10 to the source or drain region 4 within a single cell, the layout of the metal wires 8 becomes complicated, and the cell size will be restricted by the width of the metal wires 8 and the space between the wires 8.
Because the ferroelectric substance layer 6 is formed above the gate electrode 3, the cell becomes thicker and the metal wires 8 have large stepped portions, which may cause processing-oriented defects of the metal wires 8, such as the wires being open-circuited or short-circuited somewhere.